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IBM demonstrates the first sub-1nm chip using a 3D nanostack architecture with nearly 100 billion transistors

· by Pondero Newsdesk

The short version

IBM Research published results at VLSI 2026 showing a 0.7nm nanosheet chip that vertically stacks transistors in 3D, projecting 50% more performance or 70% better efficiency than its 2nm node.

IBM demonstrates the first sub-1nm chip using a 3D nanostack architecture with nearly 100 billion transistors

IBM Research published semiconductor results at VLSI 2026 on June 25 that cross the threshold every chip roadmap has been treating as a hard wall: a working transistor architecture below 1 nanometer, operating at the 0.7nm (7 angstrom) node.

What

Per IBM's newsroom, the chip packs nearly 100 billion transistors onto a fingernail-sized die, roughly twice the density of IBM's 2nm node chip announced in 2021. The architecture, called nanostack, moves beyond current GAAFET (gate-all-around) nanosheet designs by vertically stacking and staggering nanosheet transistors using 3D sequential integration. Each stacked layer can use different material combinations, which lets IBM tune performance and power independently across layers.

Published projections show up to 50% more performance or 70% greater energy efficiency compared with IBM's 2nm chips. A separate result presented at VLSI 2026 shows 40% scaling in SRAM density, which IBM says supports the high-bandwidth memory demands of AI inference workloads. IBM validated the architecture through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering, and functional CMOS inverter operation with expected switching behavior. Jay Gambetta, Director of IBM Research, described nanostack as "reinventing how chips are built" in a statement published with the press release. IBM places the earliest path to production at roughly five years from now.

The Albany, New York research facility where IBM conducted this work is also slated to receive an ASML High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, a machine required for manufacturing chips at these dimensions. Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions are named as process-development partners.

Why it matters

The 1nm barrier has been the practical limit cited by Intel, TSMC, and Samsung in their public roadmaps through 2025. A demonstrated working architecture at 0.7nm, with published CMOS inverter validation, shifts that conversation from theoretical to experimental. For AI workloads specifically, the SRAM density result is notable: tighter SRAM means more on-chip cache per die, which directly affects how much weight data a model inference engine can keep local without off-chip memory traffic, a primary bottleneck in large-model serving at scale.

Five years to production is a long horizon, and IBM has no named foundry partner for commercialization. The company no longer operates its own chip fabs at leading-edge nodes, having sold its semiconductor manufacturing business to GlobalFoundries in 2015. So the nanostack architecture needs a manufacturing partner before it reaches volume silicon. Still, the published validation at VLSI 2026 provides a credible blueprint for the next decade of scaling that the current GAAFET roadmap could not deliver past roughly 2nm.

For teams buying or building on cloud AI infrastructure today, the practical implication is a 3-5 year heads-up: the compute cost curves for AI inference will continue to drop as this architecture finds a path to volume production.

What to watch next

The immediate signal to track is a foundry partnership announcement. TSMC, Samsung Foundry, and Rapidus (the Japanese government-backed chip startup) are the most capable candidates for sub-1nm volume production. IBM has not named a commercialization partner, and it will need one before nanostack moves from Albany lab to a production wafer. A TSMC or Samsung confirmation would compress the five-year timeline; the absence of a named partner through the end of 2026 would suggest the architecture remains a research demonstration rather than a committed product roadmap.

Watch also for Intel and TSMC technical responses. Both have their own sub-2nm programs, and a credible IBM result at 0.7nm is the kind of published data point that tends to surface in competitor roadmap briefings within six to twelve months.

Sources